This invention relates to a method of producing a semiconductor integrated circuit, particularly, to an improved method of forming a separation region for semiconductor elements.
A semiconductor integrated circuit tends to be prominently enlarged in scale in accordance with increases in integration density and diversification of logic functions, with the result that the demand for high resolution of the semiconductor element reaches a sub-micron order. Naturally, it is a matter of serious concern in this field to develop an improved technique for separating the semiconductor elements for achieving the desired resolution mentioned above.
Various methods of separating semiconductor elements by using a dielectric material have hitherto been proposed for increasing the integration density, including the following:
(1) LOCOS (Local Oxidation of Silicon) method or Isoplanar method silicon substrate is selectively converted into a thick SiO.sub.2 layer for providing a region for separating semiconductor elements.
(2) IPOS (Insulation by oxidized Porous Silicon) a silicon substrate is selectively made porous, whereafter the porous region is oxidized to provide a region for separating semiconductor elements.
(3) VIP (V-groove Isolation Polycrystal backfill) method: A substrate surface is selectively etched anisotropically so as to form a V-groove, followed by oxidizing the groove surface and, then, filling the groove with polycrystalline silicon. Finally, the surface of the polycrystalline silicon layer is mechanically polished and smoothed.
Prior art method (1) mentioned above is applied in general to MOS-LSI, bipolar LSI, etc. However, method (1) involves an oxidation treatment for a long period of time under high temperatures, with the result that, in the case of bipolar LSI, an outward diffusion occurs from the buried layer, leading to a lowered withstand voltage of the pn junction. It will also invite pattern deformation due to side oxidation, thereby in the case of, for example, MOS-LSI, altering the width of the channel region which influences the characteristics of the device, leading to varied characteristics of the device. Also, in the case of etching and, then, oxidizing a silicon substrate, so-called "bird's beak" and "bird's head" are brought about, leading in some cases to breakage of the Al wiring.
Prior art method (2) is also defective in that a change in volume is brought about in the step of oxidizing the porous region, leading to strained silicon substrate, breakage of the substrate, current leakage through the pn junction, etc. As a matter of fact, prior art method (2) has not yet been put to practical use. Further, prior art method (3) leaves room for further improvement in, particularly, the precision of the surface polishing technique. Naturally, prior art method (3) is low in yield, resulting in high costs. Also, negative influences are induced into the element characteristics by the mechanical polishing. Such being the situation, proir art method (3) has not yet been put to practical use except in special cases.